Due to the fast development of communication, such as handheld telephones, research and development personnel have always striven for a frequency synthesizer that provides high frequency resolution and fast frequency switching time. However, a frequency synthesizer with these qualities has been hard to achieve.
Please refer to FIG. 1, which illustrates a conventional integer-N PLL frequency synthesizer. The PLL 100 includes a phase frequency detector 10, a charge pump 20, a loop filter 30, a VCO (voltage controlled oscillator) 40 and a divider 50. A reference signal with reference frequency (Fref) generated by a reference oscillator (not shown) and a frequency divided signal are simultaneously inputted to the phase frequency detector 10. The phase frequency detector 10 detects the phase and frequency difference between the reference signal and the frequency divided signal, and then outputs a phase difference signal to the charge pump 20. The charge pump 20 then, according to the duty cycle of the phase difference signal, generates a corresponding output current pulse into the loop filter 30. The loop filter 30 integrates and transforms the charge pump output current pulse into a control voltage to the VCO 40, where the VCO 40 adjusts its output frequency (Fvco) in accordance with the control voltage. The divider 50 receives the VCO output signal and the frequency Fvco is divided by an integer N to generate the frequency-divided signal, which is inputted to the phase frequency detector 10.
Since N is an integer, the VCO frequency (Fvco) must be an integer multiple of the reference frequency (Fref). Hence the frequency resolution of a typical integer-N PLL frequency synthesizer is relatively low.
In recent years, fractional-N frequency synthesizers have been broadly introduced. Because the average N is a fractional number, the VCO frequency (Fvco) is therefore a fractional multiple of the reference frequency (Fref). As a result, the frequency resolution can be sufficiently enhanced.
Please refer to FIG. 2, which illustrates a conventional fractional-N PLL frequency synthesizer. The time-varying integer N is controlled by the sum of a fixed integer (A) from a register 70 and a variable integer provided by the delta-sigma modulator (hereafter “ΔΣ modulator”) 60. As can be seen from FIG. 2, the ΔΣ modulator 60 has a clock input terminal and a fractional value (n) input terminal. The clock input terminal of the ΔΣ modulator 60 connects to the output terminal of the multi-modulus divider 55, while the output terminal of the ΔΣ modulator 60 connects to an adder 65. Furthermore, the output of the register 70, which stores the fixed integer A is also connected to adder 65. The division ratio N of the feedback divider is synchronously varied with its own output and equals to the output value of the adder 65.
]FIG. 3A illustrates a first-order ΔΣ modulator realized by a digital accumulator. For instance, the size of the digital accumulator 62, with a clock input terminal (CLK), a first input terminal (X), a second input terminal (Y), a summation output terminal (X+Y) and an overflow output terminal (O), is d bits. The first input terminal (X) receives a first value (n). The second input terminal (Y) connects to the summation output terminal (X+Y). The overflow output terminal (O) is the output terminal of the first-order ΔΣ modulator. For example, when n=5 and d=4, Table 1 lists the output values of the summation output terminal (X+Y) and the overflow output terminal (O) along with the increment of input clock cycles.
TABLE 1(X + Y)5101549143813271215110510154(O)00010010010010010001
According to Table 1, the summation output terminal (X+Y) and the overflow output terminal (O) repeatedly generate the same output sequence in every 16 clock cycles, where the overflow output terminal (O) toggles 5 times. Similarly, when the first value (n) is 9, the overflow output terminal (O) would toggle 9 times in every 16 clocks. Therefore, the first value (n) represents the number of times the overflow output terminal (O) toggles in every 16 clocks. The repetitive period of 16 clocks is determined by the size of the digital accumulator, that is, d=4 and 2d represents the 16 clocks. Therefore when the size of digital accumulator 62 is d bits, and the first value is n, the overflow output terminal (O) shall toggle n times in every 2d clocks, and the summation output terminal (X+Y) would generate the same output sequence in every 2d clocks. The first-order ΔΣ modulator can also be represented by the discrete time function, as illustrated by FIG. 3B. When the accumulating value exceeds a maximum value that corresponds to the size of the digital accumulator, the digital accumulator overflows and the comparator 64 produces a “1”. When the accumulating value does not exceed the maximum value, the digital accumulator does not overflow and the comparator 64 produces a “0”. In other words, the comparator 64 uses the maximum value of the digital accumulator as the threshold for comparison.
Referring to FIG. 2 again, because the clock of ΔΣ modulator 60 is decided by the output of the multi-modulus divider 55, using d=4, n=5 as example, in every 16 clocks, the overflow output terminal (O) of ΔΣ modulator 60 toggles 5 times. That is to say, in every 16 clocks, when the overflow output terminal (O) has not been toggled, the multi-modulus divider 55 divides the Fvco by A (N=A). On the other hand, when the overflow output terminal (O) is toggled, the multi-modulus divider 55 divides Fvco by A+1 (N=A+1). Therefore, the averaged Fvco is Fvco=(A+ 5/16)*Fref, which means that N is a non-integer, i.e. a fractional number “A+ 5/16.” In general, when the size of the ΔΣ modulator is d, and input value is n, it results in an averaged division ratio, N=A+n/2d. Therefore, the fractional-N phase locked loop frequency synthesizer is realized by the prior art.
The conventional fractional-N PLL frequency synthesizer illustrated in FIG. 2 requires a ΔΣ modulator 60 and a multi-modulus divider 55, which is often the most challenging part of the circuit design.